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hm5165405au-6 64m edo dram (16-mword 4-bit) 4k refresh ade-203-836b (z) rev. 2.0 nov. 10, 1997 description the hitachi hm5165405au-6 is cmos dynamic ram organized 16,777,216-word 4-bit. it employs the most advanced cmos technology for high performance and low power. hm5165405au-6 offers extended data out (edo) page mode as a high speed access mode. it has the package variations of standard 400-mil 32-pin plastic tsopii. features single 3.3 v ( 0.3 v) access time: 60 ns (max) power dissipation ? active mode: 576 mw (max) ? standby mode: 1.08 mw (max) edo page mode capability refresh cycle ? 4096 refresh cycles: 128 ms 4 variations of refresh ? ras -only refresh ? cas -before- ras refresh ? hidden refresh ? self refresh battery backup operation ordering information type no. access time package HM5165405AUTT-6 60 ns 400-mil 32-pin plastic tsop ii (ttp-32dc)
hm5165405au-6 2 pin arrangement v i/o3 i/o2 nc nc nc cas oe nc a11 a10 a9 a8 a7 a6 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc i/o0 i/o1 nc nc nc nc we ras a0 a1 a2 a3 a4 a5 v cc ss hm5165405autt series (top view)
hm5165405au-6 3 pin description pin name function a0 to a11 address input row/refresh address a0 to a11 column address a0 to a11 i/o0 to i/o3 data input/data output ras row address strobe cas column address strobe we read/write enable oe output enable v cc power supply v ss ground nc no connection* 1 notes: 1. not internally connected with die.
hm5165405au-6 4 block diagram a0 a1 to a11 timing and control column address buffers row address buffers i/o buffers i/o0 to i/o3 ras cas we oe column decoder row decoder 16m array 16m array 16m array 16m array absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t C0.5 to v cc + 0.5 ( 4.6 v (max)) v supply voltage relative to v ss v cc C0.5 to +4.6 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c
hm5165405au-6 5 recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit notes supply voltage v cc 3.0 3.3 3.6 v 1, 2 input high voltage v ih 2.0 v cc + 0.3 v 1 input low voltage v il C0.3 0.8 v 1 note: 1. all voltage referred to v ss . 2. the supply voltage with all v cc pins must be on the same level. the supply voltage with all v ss pins must be on the same level.
hm5165405au-6 6 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) hm5165405au 60 ns parameter symbol min max unit test conditions operating current* 1 , * 2 i cc1 160 ma t rc = min standby current i cc2 2 ma ttl interface ras , cas = v ih dout = high-z 300 m a cmos interface ras , cas 3 v cc C 0.2 v dout = high-z ras -only refresh current* 2 i cc3 160 ma t rc = min standby current* 1 i cc5 5 ma ras = v ih , cas = v il dout = enable cas -before- ras refresh current i cc6 140 ma t rc = min edo page mode current* 1, * 3 i cc7 120 ma t hpc = min battery backup current* 4 (standby with cbr refresh) i cc10 650 m a cmos interface dout = high-z, cbr refresh: t rc = 31.3 m s t ras 0.3 m s self refresh mode current i cc11 400 m a cmos interface ras , cas 0.2 v dout = high-z input leakage current i li C10 10 m a 0 v vin v cc + 0.3 v output leakage current i lo C10 10 m a 0 v vout v cc dout = disable output high voltage v oh 2.4 v cc v high iout = C2 ma output low voltage v ol 0 0.4 v low iout = 2 ma notes : 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less within one page mode cycle t hpc . 4. v ih 3 v cc C 0.2 v, 0 v v il 0.2 v.
hm5165405au-6 7 capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) parameter symbol typ max unit notes input capacitance (address) c i1 5 pf 1 input capacitance (clocks) c i2 7 pf 1 output capacitance (data-in, data-out) c i/o 7 pf 1, 2 notes : 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. ras and cas = v ih to disable dout.
hm5165405au-6 8 ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) * 1 , * 2 , * 17 test conditions input rise and fall time: 2 ns input levels: v il = 0 v, v ih = 3 v input timing reference levels: 0.8 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v output load: 1 ttl gate + c l (100 pf) (including scope and jig) read, write, read-modify-write and refresh cycles (common parameters) hm5165405au 60 ns parameter symbol min max unit notes random read or write cycle time t rc 104 ns ras precharge time t rp 40 ns cas precharge time t cp 10 ns ras pulse width t ras 60 10000 ns cas pulse width t cas 10 10000 ns row address setup time t asr 0ns row address hold time t rah 10 ns column address setup time t asc 0ns column address hold time t cah 10 ns ras to cas delay time t rcd 20 45 ns 3 ras to column address delay time t rad 14 30 ns 4 ras hold time t rsh 15 ns cas hold time t csh 48 ns 21 cas to ras precharge time t crp 5ns oe to din delay time t oed 15 ns 5 oe delay time from din t dzo 0 ns 6 cas delay time from din t dzc 0 ns 6 transition time (rise and fall) t t 250ns7
hm5165405au-6 9 read cycle hm5165405au 60 ns parameter symbol min max unit notes access time from ras t rac 60 ns 8, 9 access time from cas t cac 15 ns 9, 10, 16 access time from address t aa 30 ns 9, 11, 16 access time from oe t oea 15ns9 read command setup time t rcs 0ns read command hold time to cas t rch 0 ns 12 read command hold time from ras t rchr 60 ns read command hold time to ras t rrh 0 ns 12 column address to ras lead time t ral 30 ns column address to cas lead time t cal 18 ns cas to output in low-z t clz 0ns output data hold time t oh 3 ns 20 output data hold time from oe t oho 3ns output buffer turn-off time t off 15 ns 13, 20 output buffer turn-off to oe t oez 15ns13 cas to din delay time t cdd 15 ns 5 output data hold time from ras t ohr 3 ns 20 output buffer turn-off to ras t ofr 15 ns 13, 20 output buffer turn-off to we t wez 15ns13 we to din delay time t wed 15 ns ras to din delay time t rdd 15 ns
hm5165405au-6 10 write cycle hm5165405au 60 ns parameter symbol min max unit notes write command setup time t wcs 0 ns 14 write command hold time t wch 10 ns write command pulse width t wp 10 ns write command to ras lead time t rwl 15 ns write command to cas lead time t cwl 10 ns data-in setup time t ds 0ns data-in hold time t dh 10 ns read-modify-write cycle hm5165405au 60 ns parameter symbol min max unit notes read-modify-write cycle time t rwc 149 ns ras to we delay time t rwd 78 ns 14 cas to we delay time t cwd 33 ns 14 column address to we delay time t awd 48 ns 14 oe hold time from we t oeh 15 ns refresh cycle hm5165405au 60 ns parameter symbol min max unit notes cas setup time (cbr refresh cycle) t csr 5ns cas hold time (cbr refresh cycle) t chr 10 ns we setup time (cbr refresh cycle) t wrp 0ns we hold time (cbr refresh cycle) t wrh 10 ns ras precharge to cas hold time t rpc 0ns
hm5165405au-6 11 edo page mode cycle hm5165405au 60 ns parameter symbol min max unit notes edo page mode cycle time t hpc 25 ns 19 edo page mode ras pulse width t rasp 100000 ns 15 access time from cas precharge t cpa 35 ns 9, 16 ras hold time from cas precharge t cprh 35 ns output data hold time from cas low t doh 3 ns 9 cas hold time referred oe t col 10 ns cas to oe setup time t cop 10 ns read command hold time from cas precharge t rchc 35 ns write pulse width during cas precharge t wpe 10 ns oe precharge time t oep 10 ns edo page mode read-modify-write cycle hm5165405au 60 ns parameter symbol min max unit notes edo page mode read- modify-write cycle time t hprwc 68 ns we delay time from cas precharge t cpw 54 ns 14 refresh refresh ) parameter symbol max unit notes refresh period t ref 128 ms 4096 cycles
hm5165405au-6 12 self refresh mode hm5165405au 60 ns parameter symbol min max unit notes ras pulse width (self refresh) t rass 100 m s ras precharge time (self refresh) t rps 110 ns cas hold time (self refresh) t chs C50 ns notes: 1. ac measurements assume t t = 2 ns. 2. an initial pause of 200 m s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh or cas -before- ras refresh). 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t oed or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 1 ttl loads and 100 pf. 10. assumes that t rcd 3 t rcd (max) and t rcd + t cac (max) 3 t rad + t aa (max). 11. assumes that t rad 3 t rad (max) and t rcd + t cac (max) t rad + t aa (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max), t oez (max), t wez (max) and t ofr (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), and t awd 3 t awd (min), or t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t rasp defines ras pulse width in edo page mode cycles. 16. access time is determined by the longest among t aa , t cac and t cpa . 17. all the v cc and v ss pins shall be supplied with the same voltages. 18. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. 19. t hpc (min) can be achieved during a series of edo page mode write cycles or edo page mode read cycles. if both write and read operation are mixed in a edo page mode ras cycle (edo page mode mix cycle (1), (2)), minimum value of cas cycle (t cas + t cp + 2 t t ) becomes greater than the specified t hpc (min) value. the value of cas cycle time of mixed edo page mode is shown in edo page mode mix cycle (1) and (2). 20. data output turns off and becomes high impedance from later rising edge of ras and cas . hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh and between t ofr and t off .
hm5165405au-6 13 21. t csh (min) can be achieved when t rcd t csh (min) C t cas (min). 22. please do not use t rass timing, 10 m s t rass 100 m s. during this period, the device is in transition state from normal operation mode to self refresh mode. if t rass > 100 m s, then ras precharge time should use t rps instead of t rp . 23. cbr burst refresh or 4096 cycles of distributed cbr refresh with 15.6 m s interval should be executed within 64 ms immediately after exiting from and before entering into the self refresh mode. 24. repetitive self refresh mode without refreshing all memory is not allowed. once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 25. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hm5165405au-6 14 timing waveforms* 25 read cycle ras address we dout oe din t rc row column t rcs t rch t cdd t dzc high-z dout t dzo t oed t rac t oea t aa t cac t clz t oh t off t oho t oez cas t rdd t wed t ofr t ohr t wez t ras t cas t rp t csh t rcd t rsh t crp t t t rad t ral t cal t asr t asc t cah t rchr t rrh t rah
hm5165405au-6 15 early write cycle ras address we din dout t rc * t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din t wcs wcs (min) high-z* t cas
hm5165405au-6 16 delayed write cycle * 18 address cas ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t oed t oeh t oep t clz t oez high-z invalid dout din high-z
hm5165405au-6 17 read-modify-write cycle * 18 address ras din dout oe we t rwc t ras t rp t crp t cas t rcd t t t rad t asr t rah t asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t oed t oeh t oea t cac t aa t rac t oho t oez t clz dout high-z cas t oep
hm5165405au-6 18 ras -only refresh cycle ras cas address dout high-z row t rc t rp t ras t t t crp t rpc t crp t asr t rah t off t ofr
hm5165405au-6 19 cas -before- ras refresh cycle ras cas we dout address t rc t rp t ras t rpc t csr t chr t rpc t crp t cp t wrh t wrp t cp t t t off t ofr high-z t rp
hm5165405au-6 20 hidden refresh cycle din oe dout we address ras t rc t rc t rc t rp t ras t rp t ras t rp t ras t t t rcd t rsh t chr t crp t rad t ral t cah t asc t rah t asr t cdd t dzc t oed t oez t oho t off t oh t cac t aa t rac t clz dout column row t oea high-z t rch t rrh cas t wed t rdd t wez t ofr t ohr t rcs t dzo
hm5165405au-6 21 edo page mode read cycle (1) din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t dzc t cdd t rdd high-z t ofr t oez t oho t off t oh t ohr t t col t t cpa t aa t cac t cac t oea t aa t rac t aa t cac t cpa t t oez t oea t oez t aa t cac t t rasp cop t rp t cas t cas t cas t cal t csh t hpc t hpc crp t t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wed t ral row dout 2 dout 2 dout 4 dout 1 t cas t rcs t t rcs dout 3 t oho t t cprh t hpc t oea t wez dzo t oed oho doh rch t wpe t rchr t cal t cal t cal t rsh t rchc cpa asc t oep t oep
hm5165405au-6 22 edo page mode read cycle (2) din oe we address t dzc t cdd t rdd high-z t ofr t oez t oho t off t oh t ohr t t col t t cpa t aa t cac t cac t oea t aa t rac t aa t doh t t oez t t oez t aa t cac t cop t asr t rah t t cah t asc t cah t cah t asc t cah t asc t wed t ral dout 2 dout 4 dout 1 t rcs t oho t oea dzo t oed t doh t cac t rchc cpa asc ras cas t cp t cp t cp t t t rch t rrh t rasp t rp t cas t cas t cas t csh t hpc t hpc t hpc crp t t cas t cal t cal t cal t cal t rsh dout dout 3 dout 2 oho oea t cpa column 2 column 1 row column 3 column 4 t oep t oep
hm5165405au-6 23 edo page mode early write cycle * t wcs wcs (min) ras address we din dout t rasp t rp t t t csh t hpc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah t wch t wcs t wch t wcs t wch t wcs t dh t ds t dh t ds t dh t ds din 1 din 2 din n high-z* t row column 1 column 2 column n cas
hm5165405au-6 24 edo page mode delayed write cycle * 18 we din oe dout address ras t rasp t rp t crp t rsh t cas t hpc t cas t cas t csh t rcd t t t cp t cp t asc t cah t asc t cah t asc t cah t rad t asr t rah t rcs t rcs t rcs t rwl t cwl t cwl t cwl t wp t wp t wp t dzc t ds t dzc t ds t ds t dzc t dh t dh t dh t dzo t oed t dzo t oed t dzo t oed t oeh t oeh t oeh t oez t clz t clz t oez t clz t oez invalid dout invalid dout invalid dout din 1 din 2 din n column n column 2 column 1 row high-z cas t oep t oep t oep
hm5165405au-6 25 edo page mode read-modify-write cycle * 18 we din oe dout address ras t rasp t crp t cp t hprwc t t t rcd t cas t cp t cas t cas t rad t asr t asc t asc t asc t rah t cah t cah t cah t cwl t cpw t cwl t cpw t cwl t rwd t awd t awd t awd t cwd t rcs t cwd t rcs t cwd t rcs t wp t wp t wp t ds t dzc t ds t dzc t ds t dzc t dh t dh t dh t dzo t dzo t dzo t oeh t oep t oep t oep t oeh t oeh t aa t rac t oez t clz dout n dout 2 dout 1 din 1 din 2 din n column n column 2 column 1 t rp row t rwl t oho t oea t cac t oez t clz t oho t oea t cac t cpa t oez t clz t oho t oea t cac t cpa high-z t oed t oed t oed aa t aa t t rsh cas
hm5165405au-6 26 edo page mode mix cycle (1) * 19 oe dout we address ras cas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t cpa t oez t aa t oea t t rasp t rp t cas t cas t cas crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t cah t ral t cal row dout 2 dout 4 cpa t cas t wcs dout 3 t t t wp t wch t wed t wez t ds t dh t ds t dh din 3 din 1 t oea t oed t oep t cac t asc t cpw t awd oho t cal t rcs t rcs t csh t rcd t rsh doh asc t din
hm5165405au-6 27 edo page mode mix cycle (2) * 19 din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t oez t t oea t t rasp t rp t cas t cas t cas t csh crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t asc t cah t ral t rcs row dout 1 dout 4 cpa t cas dout 3 t oho t wed t wez t ds t dh t ds t din 3 din 2 t oea t t cac t cpw t rch t rcs t wch t rac t oed t col t oea t oho t oez t dh oed t rcs t cal t cal t cal t cal t rcd t rchr t wcs t rsh t wp t asc aa t oep t oep cop
hm5165405au-6 28 self refresh cycle * 22, 23, 24 ras dout t rp t rass t rps t rpc t t t cp t csr t chs t crp t off t ofr high-z cas t wrp t wrh we
hm5165405au-6 29 package dimensions hm5165405autt series (ttp-32dc) 1.27 0.21 m 0.42 0.08 0.10 10.16 20.95 21.35 max 17 16 32 1 1.20 max 0 ?5 0.13 0.05 0.145 0.05 11.76 0.20 1.15 max hitachi code jedec code eiaj code weight (reference value) ttp-32dc mo-133ca ? 0.51 g 0.40 0.06 0.125 0.04 unit: mm 0.50 0.10 0.68 0.80 dimension including the plating thickness base material dimension
hm5165405au-6 30 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm5165405au-6 31 revision record rev. date contents of modification drawn by approved by 1.0 sep. 30, 1997 initial issue m. tsunozaki m. saeki 2.0 nov. 10, 1997 deletion of hm5165405auj series (cp-32dc) deletion of hm5165405autt-5/-7

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